logic gate

英 [ˈlɒdʒɪk ɡeɪt]

美 [ˈlɑːdʒɪk ɡeɪt]

n.  逻辑门，逻辑闸(以两种方式之一对所输入数据进行输出的电子开关)

牛津词典

noun

• 逻辑门，逻辑闸（以两种方式之一对所输入数据进行输出的电子开关）
  an electronic switch that reacts in one of two ways to data that is put into it. A computer performs operations by passing data through a very large number of logic gates .

英英释义

noun

• a computer circuit with several inputs but only one output that can be activated by particular combinations of inputs
  Synonym:gate

双语例句

• Josephson junction logic gate
  约瑟夫逊结逻辑门电路
• Use the quantum logic gate for implementing multi-purpose quantum cloning machine.
  利用通用量子门实现多用途量子克隆机的方案。
• And a computer inside actually assembles with many digital circuits, while digital circuits can be seen as the logic gate network that achieve by the electronic devices.
  而一台电子计算机的内部实际上是由许许多多个数字电路组成，而数字电路可以看作是用电子器件实现的逻辑门网络。
• Each particle in the system acts like the logic gate of a computer.
  系统中每个粒子的作用类似电脑里的逻辑闸。
• Implication Logic Function and Implication Logic Gate
  蕴函逻辑函数和蕴函逻辑门的研究
• Reversible logic gate cascade is an important part of reversible logic synthesis.
  可逆逻辑门级联是可逆逻辑综合的重要组成部分。
• The special Flip-Flop, combination logic gate and improved topology of Prescaler, enable the Prescaler to intensify the low power-high speed tradeoff.
  其中，采用了特殊的D触发器和组合逻辑门结构，改进了预置数分频器结构，能够使分频器工作在低功耗、高速度之间有比较好的折衷。
• This paper presents the conversion from dynamic logic gate to Markov chain, the solution of dynamic subtree top event failure probability and the method of obtaining the failure mode of subsystem using Markov model, that is sequence cutsets of the dynamic subtree.
  论文研究了动态逻辑门向马尔可夫链的转化方法，利用马尔可夫链法求解动态子树顶事件概率，以及通过马尔可夫状态转移图直接找出子系统的故障模式和薄弱环节，即得到动态子树的顺序割集。
• This paper introduces a new concept of implication logic function and implication logic gate. The implication logic gate can be used as a basic unit in a large-scale digital IC to simplify circuitry and reduce power dissipation.
  本文引出蕴函逻辑函数和蕴函逻辑门的新概念，利用蕴函逻辑门作为大规模数字集成电路的基本单元可以简化电路，减小电路的功耗。
• This paper introduces a new structure of numeral multilier: using one-level logic gate structure to realize array numeral multiplier, and using cmos technology to realize 8 × 8 ultraspeed array numeral multiplier with a new structure.
  本文介绍了一种新的数码乘法器结构：采用一级逻辑门结构实现阵列式数码乘法器，并采用CMOS工艺技术实现新结构的8×8位超高速阵列式数码乘法器。